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ABSTRACT

AN ALGORITHM IS DESCRIBED WHICH REDUCES SYSTEM OVERHEAD AND ENHANCES SYSTEM PERFORMANCE BY RECORDING (TRANSFER FROM MAIN STORE TO DISK) ROLLED-OUT PASSES IN A &#34;PAGE VALID&#34; STATE, I.E. THE COPY OF THE PAGE OF DATA IS STILL IN MAIN (OR REAL) STORED AND ACCESSIBLE FOR PROCESSING DURING ROLL-OUT. THIS METHOD ELIMINATES PAGE FAULTS (A DETERMINING THAT THE DESIRED PAGE IS NOT AVAILABLE FOR ACCESS IN MAIN STORE) DURING AND AFTER THE ROLL-OUT CYCLE. WHEN THE RECORDING IS COMPLETED, THE &#34;CHANGE&#34; BIT (SOMETIMES CALLED &#34;ALTER&#34; BIT) OF THE PAGE IS TESTED TO INSURE THAT THE RECORDING IS ACCURATE (THE COPY IN MAIN STORE COPY NOT BEEN ALTERED DURING ROLL-OUT). IF THE MAIN STORE COPY OF THE ROLLED-OUT PAGE HAS BEEN ALTERNED, ANOTHER PAGE IS SELECTED FOR ROLL-OUT. IF THE RECORDING IS ACCURATE AND A NEW PAGE IS WATING TO BE ROLLED IN, THE MAIN STORE COPY OF THE ROLLED-OUT PAGE IS INVALIDATED, AND ROLL-IN OF A NEW PAGE OVERLYING THE ROLLED-OUT PAGE IS INITATED. THUS, THE PAGE IS HELD VALID AND AVAILABLE UNTIL JUST PRIOR TO ITS BEING OVERLAYED WITH A NEW PAGE OF DATA.

DEFENSlVE PU LlCATlQN UNITED sTATEs PATENT AND TRADEMARK OFFICE Published at the request of the applicant or owner in accordance with the Notice of Dec. 16, 1969, 869 0.G. 687. The abstracts of Defensive Publication applications are identified by distinctly numbered series, and are arranged chronologically. The heading of each abstract indicates the number of pages of specification, including claims and sheets of drawings contained in the application as originally filed. The files of these applications are available to the public for inspection and reproduction may be purchased for 30 cents a sheet. ,v

Defensive Publication applications have not been examined as to the merits of alleged invention. The Patent and Trademark Oflice makes no assertion as to the novelty of the disclosed subject matter.

PUBLISHED OCTOBER 7, 1975 T939304 ALGORITHM FOR PAGE RECLAMATION VIA CHANGE BIT RECORDING IN RELOCATABLE CPU ENVIRONMENTS Warren J. Kelley, Berkshire, and Lawrence E. Larson, Vestal, N.Y., assignors to International Business Machines Corporation, Armonk, N.Y. Continuation of abandoned application Ser. No. 274,785, July 24, 1972. This application Oct. 18, 1973, Ser. No.

Int. Cl. Glldf 13/00 U.S. Cl. 444-1 4 Sheets Drawing. 25 Pages Specification USMil EDlIlNG SYSIEK VIM) liEiiFlAllW HASUE scmuza i mom lUINrHAlDiL INTERN" NANBLER An algorithm is described which reduces system overhead and enhances system performance by recording (transfer from main store to disk) rolled-out pages in a page valid state, i.e. the copy of the page of data is still in main (or real) store and accessible for processing during roll-out. This method eliminates page faults (a determination that the desired page is not available for access in main store) during and after the roll-out cycle. When the recording is completed, the change bit (sometimes called alter bit) of the page is tested to insure that the recording is accurate (the copy in main store has not been altered during roll-out). If the main store copy of the rolled-out page has been altered, another page is selected for roll-out. If the recording is accurate and a new page is Waiting to be rolled in, the main store copy of the rolled-out page is invalidated, and roll-in of a new page overlaying the rolled-out page is initiated. Thus, the page is held valid and available until just prior to its being overlayed with a new page of data.

Oct. '7, 1975 ALGORITHM FOR PAGE RECLAMATION WJ. KELLEY et a1.

VIA CHANGE BIT RECORDING IN RELOCATABLE CPU ENVIRONMENTS Original Filed Oct. 18, 1973 Sheet 2 of 4 SEGMENT TABLE A5 PAGE TABLE PAGE TABLE I E L KEY sToBE TNvALTBATE BITS TB ALTERREE 2$ BIT BLT A 5 L, fi i0 12 i1 1 210 200 A PAGE FRAME AVAILABLE ouEuEHEAoEBl I/oTAsA TABLE 216 TABLE CPU ENTRY INUSEQUEUEHEADER ENTRYN #215 21 f LOAD BUFFER 20 REG ADDR TRANSFER BUFFER SAR VIRTUAL 222 iiiii BEss ADDRESS PK; 2

I/O TASK TABLE 200 CHANNEL/ sAvEB SAVED VIRTUAL PAGE POST CHAIN PGM AREA PFTE PSW REGISTERS REQUESTED POINTER TASK EQB TASKZ E E A A A FIG. 5

PAGE BEING REA Get. 7, 1975 W.J. KELLEY et a1. T939,004

ALGORITHM FOR PAGE RECLAMATION VIA CHANGE BIT RECORDING IN RELOCATABLE CPU ENVIRONMENTS Original Filed Oct. 18, 1973 Sheet 3 of 4 PAGE FAULT F IG. 3

PAGE FAULT PRocEss SAVE STATUS TO POST CHAIN COMPLETE STATUS 106 ,I09 R0 R1 2 GET FRAME A I F UNUSED N =1 PUT FRAME 0N RAMEs AVA|LR%M FRAME ALTER BIT IN USE Q N Y =0 1 115 {58% INVALIDATE PAGE CURRENTLY IN FRAME I MG /H7 START 1/0 HSET ALTER B|T=0 PAGE READ OF NEW PAGE H5 118 I GEI FRAME g VALIDATE FRGM IN USE 0 PAGE PUT FRAME ON IN USEQ sEI ALTER BIT ,122 125 121 I20 TOZERO FRAME FIX OOUNT=0 PGsI EGR -FR0M v POST CHAIN 24 PUT FRAME 0M AVAIL o START I/O Y PAGE WRITE T2?) WATT FOR I/O COMPLETE RETURN I/O SQHED RETURN I/O SCHED Oct. 7, 1975 W.J. KELLEY et a1.

ALGORITHM FOR PAGE RECLAMATION VIA CHANGE BIT RECORDING IN RELOCATABLE CPU ENVIRONMENTS Original Filed Oct. 18, 1973 AVAILABLE OUEUE HEADER FIRST LAST OUEUE POINTER POINTER COUNT GET FRAME FROM IN usE QUEUE 154 PUT FRAME ON AVAIL QUEUE I35 SET PAGE ALTERED BIT T0 ZERO WRITE WAS Y ALTERED PAGE FIXED PAGE N m I /I59 NAIL PUT FRAME 0N FoR AVAIL QUEUE COMPL v RETURN TO PAGE WRITE PROCESS 1/0 R C FIG. 4

F I G. 6 T

Sheet 4 of 4 PAGE FRAME TABLE 215 PAGE FRAME TABLE ENTRY PFTE) FRAME O CHAIN I 9I L L E R LE REARAEEE FRAMFA PAGE! KEY FRAME N FIG. 7

IN USE OUEUE HEADER FIRST LAST OUEUE POINTER POINTER COUNT PAGE FRAME TABLE 

